Power Line Compensation

Closed Loop Gain of Op Amp in Inverting and non-inverting Configurations

IC Fabrication Assignment 1

IC Fabrication Process Assignment 1

1. Explain in detail how Integrated Circuits are classified?
2. What are the four basic layers every Integrated Circuits possess? State their purpose?
3. List out various processes involved in the fabrication of Integrated circuits using Planar method?
4. Discuss in detail the Silicon Wafer preparation with neat sketches?
5. With the basic chemical reaction involved in the process of epitaxial growth explain the process with necessary illustrations?
6. What molecular form the n and p type of impurities are administered in epitaxial growth?
7. Explain the atmosphere present in the reaction chamber meant for epitaxial growth?
8. State the significance of oxidation layer in IC fabrication process?
9. Explain the oxidation process involved in IC fabrication with a neat illustration of the reaction chamber?
10. State the methods preferred for thin and thick oxide growth?
11. Explain a) Contact Printing and b) Proximity Printing methods used in Photolithography process with neat illustrations? Also state their pros and cons?
12. ON what factors does the critical dimension in Shadow printing method depend on? Write the controlling expression.
13. What are photo resists? How are they classified? Explain them.
14. Explain briefly the following methods of lithography. 1) Electron Beam Lithography, 2) Extreme ultraviolet Lithography, 3) X-Ray Lithography and 4) Ion Beam Lithography.
15. What are the various elemental forms of impurities used in diffusion process of IC fabrication?
16. What are the factors which affect the depth of diffusion in diffusion process?
17. Explain in detail a) Thermal Diffusion technique and b) Ion implantation technique
18. Draw the doping concentration as a function of depth of diffusion and profile of dopant distribution in the technique stated in Question 18.
19. State the chemical reaction taking place in Dry and Wet oxidation process?
20. What is meant by etching? Explain briefly a) Wet Chemical etching and b) Dry etching.

Semiconductor Physics Part 1

My Research

My Research on Photovoltaic Applications

1. J.S. Christy Mano Raj, A. Ebenezer Jeyakumar, "A Novel Maximum Power Point Tracking Technique for Photovoltaic Module Based on Power Plane Analysis of I–V Characteristics," IEEE Transactions on Industrial Electronics, vol.61, no.9, pp.4734-4745, Sept. 2014. ISSN: 0278-0046
   http://dx.doi.org/10.1109/TIE.2013.2290776
   
   
2. J.S. Christy Mano Raj, A. Ebenezer Jeyakumar,"A two stage successive estimation based maximum power point tracking technique for photovoltaic modules, Solar Energy, Volume 103, May 2014, Pages 43-61, ISSN 0038-092X.
   http://dx.doi.org/10.1016/j.solener.2014.01.042
   
   
3. R. Balasankar, G. Tholkappia Arasu, J.S. Christy Mano Raj,"A global MPPT technique invoking partitioned estimation and strategic deployment of P&O to tackle partial shading conditions", Solar Energy, Volume 143, Feb 2017, Pages 73-85, ISSN 0038-092X.
   http://dx.doi.org/10.1016/j.solener.2016.12.018

Review-1

Review Questions in BJT - Part1

1. Explain the reason why the characteristic curves in the output characteristics of CB configuration are flat and those curves in CE configuration are having a slope?
2. In which configuration a forward biasing voltage is required to  reduce the collector current to zero. State the reason.
3. Why the cut-off region in the CE configuration is not well defined?
4. Why the input characteristic of CC configuration is quite different from those of CB and CE configurations?
5. Explain briefly the method to obtain the Early voltage from the output characteristics of a BJT?
6. State the applications of CB, CE and CC configurations and also elucidate which configuration is profusely used and why?
7. What factors facilitates the use of hybrid parameters to analyze BJT?
8. List out the consequences of Early effect?
9. State the reason for increase in I_B for a given value of V_BE with the increase in V_CE in the input characteristics of a CE configuration?
10. Draw the construction of a BJT precisely and annotate with the doping profile of various layers?
11. State the reasons for such construction in Q10?
12. State the reasons for such doping profiles in Q10?
13. For a certain transistor, I_B=20µA; I_C=2mA and β=100 then compute I_CB0.
14. A particular BJT has a value of α=0.95, determine the values of β and γ.
15. State the constituents of collector current in a BJT and state their causes?
16. Derive the current gain characteristics for V_CE=6V from the CE output characteristics in
    Figure-1.

    

    Figure 1

Common Base BJT

Summary about the lecture on 19-08-2014

Common Base Input Characteristics

• It is essentially the characteristics of a FB PN junction
• The input characteristics shifts towards the ordinate when the collector-base reverse bias voltage is increased, because as the |V_CB| increases the depletion region in the J_C deeply penetrates into the base region and reduces the effective base width causing an increase in the emitter current I_E. Hence for a given value of |V_EB| the input current increases with increase in |V_CB|.

Common Base Output Characteristics

• I_C is almost equal to I_E.
• I_C appears to be almost constant when V_CB is increased. This is due to the fact that with I_E held constant, the increase in I_C due to the reduction in the effective base width on account of increase in V_CB is so small and noticeable only at large values of V_CB. Hence the output curves appears to be almost horizontal.
• It is noteworthy from the output characteristics, that even when the potential V_CB is zero, the collector current I_C still flows. This is due to the fact that there exists an inherent barrier voltage across the J_C, even when the external reverse bias voltage V_CB is zero. This inherent barrier voltage aids the flow of I_C, because the electric field established in the J_C acts in such a direction to pull the minority charge carriers in the base region into the collector region constituting the current I_C. Hence in order to reduce the collector current I_C to zero it is essential to apply a forward biasing voltage to the junction J_C.
• In the cut-off region, the magnitude of the current I_CB0 is so small such that the curve, corresponding to I_E=0, seems virtually lies on the horizontal axis. Remember that the current I_CB0 is sensitive to temperature.

References:

David A. Bell, Electronic Devices and Circuits - 5Ed, Oxford University Press, New Delhi.

Robert L. Boylestad and Louis Nashelsky, Electronic Devices and Circuit Theory - 10Ed, Pearson, New Delhi.